With the continuous scaling down of the feature size of metal–oxide–semiconductor field-effect transistor (MOSFET), the switching speed, density and functionality of integrated circuits have been improved greatly. But further reducing the device dimensions will increase the leakage current, which results in increased power consumption. The higher power consumption under low supply voltage results from the not so steep subthreshold swing (SS) of MOSFET, with a 60 mV/decade limit at room temperature. In order to solve this problem, new devices such as tunneling FET (TFET)^[1–4] and impact ionization FET^[5] have been proposed. TFET benefits from the quantum mechanical band-to-band tunneling, which is different from the thermal injection of carriers in MOSFET, and can obtain SS beyond the 60 mV/decade limitation.^[6,7]

The on-state current I_ON of TFET is determined by the tunneling probability, and is much lower than that of MOSFET. The Wentzel–Kramer–Brillouin approximation provides a way to calculate the tunneling probability T_WKB:

In this paper, we study the cylindrical surrounding-gate GaAs_x Sb_1−x/In_yGa_1−yAs heterojunction TFET with gate-drain underlap by numerical simulation. The effects of device parameters and resonant tunneling on the performance of the device are investigated.

The designed structure is a lateral n-type cylindrical SG-TFET which is shown in Fig. 1. The P⁺ source region is GaAs_xSb_1−x with carbon-doped concentration N_A, the channel is undoped In_yGa_1−yAs, the N⁺ drain region is In_yGa_1−yAs with silicon-doped concentration N_D, and the dielectric material used as gate oxide layer is HfO₂. R is the channel radius, L_g is gate length, and L_underlap represents the underlap length between the gate and the drain. Unless otherwise specified, the channel length L_ch is 20 nm, the oxide thickness t_ox is 2 nm, L_underlap is equal to 10 nm, R is 7 nm, and x and y are equal to 0.35 and 0.7, respectively. The three-dimensional (3D) device simulator Sentaurus^[16] is used for simulation, and the dynamic non-local band-to-band tunneling model is activated for current calculation. Besides, under the assumption of high doping concentration in the source and drain, the band-gap narrowing model is enabled and Shockley–Read–Hall recombination model is also included. In order to consider the effect of interface trap on band-to-band tunneling in TFET, the trap-assisted tunneling model is also activated.

Fig. 1.

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	Fig. 1. Schematic of SG-TFET with gate–drain underlap.

Figure 2 shows the influence of source doping concentration on the characteristics of the heterojunction SG-TFETs. From Fig. 2, it can be observed that, by increasing N_A, there is enhancement in I_ON which results from the fact that a higher N_A will make the band steeper and enhance the electric field between the source and channel as shown in Fig. 3, thus tunneling probability increases. However, at V_DS = 0.5 V and V_GS − V_OFF = 0.5 V, where V_OFF is the gate voltage corresponding to I_OFF = 10pA/μm, I_ON increases more than 30 times when N_A varies from 10¹⁹ cm⁻³ to 5 × 10¹⁹ cm⁻³, much larger than the two-fold enhancement when N_A varies from 5 × 10¹⁹ cm⁻³ to 10²⁰ cm⁻³. The smaller increase in I_ON in the latter case results from the higher degeneration of the source region at higher doping concentration, which makes the Fermi level E_FS fall below the valence band maximum E_V in the source region and electrons partially occupy the states in the valence band between E_V and E_FS, resulting in reduced paired-tunneling states and thus smaller increase in I_ON.^[17] Figure 4 shows the dependences of transfer characteristics on N_D. It can be seen that N_D hardly influences the on-state performance, since I_ON is primarily controlled by the tunneling junction between the source and channel. Nevertheless, I_OFF increases with increasing N_D because of the ambipolar behavior.^[18] From Figs. 2 and 4, in contrast to MOSFETs, the current of TFET does not change linearly with gate voltage on a semi-logarithmic scale, which results from the band-to-band tunneling mechanism leading to the complex dependences of the tunneling current on energy band profile and available quantum states. The dependence of SS on N_D is plotted in Fig. 5. SS is lower than 60 mV/decade for a drain current range of more than 5 orders of magnitude, and achieves a minimum of 30 mV/decade when N_D is equal to 10¹⁸ cm⁻³. It is evident that SS degrades as N_D increases.

Fig. 2.

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	Fig. 2. Plots of drain current versus gate voltage for different values of carbon-doped concentration NA at VDS = 0.5 V and ND = 5 × 1018 cm−3.

Fig. 3.

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	Fig. 3. Plots of electric field versus distance along the channel for different values of carbon-doped concentration NA at VGS − VOFF = 0.5 V, VDS = 0.5 V, and ND = 5 × 1018 cm−3.

Fig. 4.

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	Fig. 4. Variations of drain current with gate voltage for different values of silicon-doped concentration ND at VDS = 0.5 V and NA = 1020 cm−3.

Fig. 5.

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	Fig. 5. Plots of SS versus drain current for different values of silicon-doped concentration ND at VDS = 0.5 V and NA = 1020 cm−3.

The influences of the gate–drain underlap L_underlap on the characteristics of SG-TFET are given in Fig. 6. It can be seen that I_ON is scarcely affected by L_underlap, but I_OFF decreases with increasing L_underlap. When V_DS = 0.5 V and V_GS = − 0.3 V, I_OFF decreases about 300 times as L_underlap varies from 0 nm to 10 nm. In the TFET with gate–drain underlap, there is a high-resistance region in the non-gated channel region which makes the electrical field reduced at the channel–drain junction. As a result, the ambipolar behavior which makes the main contribution to I_OFF is mitigated, thus I_OFF is reduced. Because the high-resistance region is near the drain, the electric field in the source–channel tunneling junction is not influenced by L_underlap. I_ON is controlled by the source–channel tunneling junction, so I_ON is insensitive to L_underlap. Figure 7 gives the dependences of SS on L_underlap. The advantage of the gate–drain underlap is more evident. When L_underlap is 10 nm, SS is lower than the thermal limitation 60 mV/decade of MOSFET for more than 2-decade drain current. Besides, the gate–drain underlap also reduces the area of gate capacity, thus reducing the gate delay.^[19]

Fig. 6.

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	Fig. 6. Curves of drain current versus gate voltage for different values of Lunderlap at VDS = 0.5 V, Lg = 10 nm, NA = 1020 cm−3, and ND = 5 × 1018 cm−3.

Fig. 7.

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	Fig. 7. SS versus drain current for different values of Lunderlap at VDS = 0.5 V, Lg = 10 nm, NA = 1020 cm−3, and ND = 5 × 1018 cm−3.

Figure 8 presents the transfer characteristics of SG-TFETs at different values of L_g, in which there is no gate–drain underlap. The plot indicates that increasing gate length results in the diminution of I_OFF, but unnoticeable change of I_ON. When L_g is reduced from 15 nm to 10 nm, due to the direct tunneling from the source to the drain, I_OFF increases more than 2 orders of magnitude at V_DS = 0.5 V and V_GS = − 0.3 V, which is much larger than the increment when L_g is changed from 20 nm to 15 nm. The weak dependence of I_ON on L_g is due to the fact that the current in TFET results from the quantum tunneling at the source–channel junction. Figure 9 shows the variations of SS with drain current at different gate lengths. SS decreases with increasing L_g and reaches a minimum value of 27.7 mV/decade when L_g is 20 nm. The current range for SS below 60 mV/decade almost reaches 6 decades.

Fig. 8.

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	Fig. 8. Variations of drain current with gate voltage for different values of gate length Lg at VDS = 0.5 V, NA = 1020 cm−3, and ND = 1018 cm−3.

Fig. 9.

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	Fig. 9. Variations of SS with drain current for different values of gate length Lg at VDS = 0.5 V, NA = 1020 cm−3, and ND = 1018 cm−3.

The band alignment can be designed through modulating the alloy compositions of GaAs_x Sb_1−x and In_yGa_1−yAs to easily obtain better device performances. Figures 10 and 11 depict the transfer and SS characteristics of SG-TFETs with different alloy compositions (x = 0.5, y = 0.53 and x = 0.4, y = 0.65), at which GaAs_x Sb_1−x and In_yGa_1−yAs are lattice-matched, and Eb_eff values are 0.5 eV and 0.31 eV, respectively.^[13,20] Here, I_ON is determined at V_DS = 0.5 V and V_GS–V_OFF (at I_OFF = 1 nA/μm) = 0.5 V. I_ON increases from 33 μA/μm to 103 μA/μm, more than 3 times, when Eb_eff varies from 0.5 eV to 0.31 eV as shown in Fig. 10. Reducing Eb_eff is an effective way to enhance I_ON, because smaller Eb_eff makes it much easier for electrons to tunnel in the n-type TFET. The simulation shown in Fig. 11 demonstrates that SS becomes better with the scaling down of Eb_eff. We can obtain higher drain current and smaller SS at the same time due to the various band alignments in GaAs_x Sb_1−x/In_yGa_1−yAs system, so the mixed-As/Sb material system is attractive for low-power applications.

Fig. 10.

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	Fig. 10. Curves of drain current versus gate voltage for different material compositions (x = 0.5, y = 0.53, Ebeff = 0.5 eV and x = 0.4, y = 0.65, Ebeff = 0.31 eV) in (dashed) linear and (solid) log scales at VDS = 0.5 V, NA = 1020 cm−3, and ND = 1018 cm−3.

Next, the effect of the resonant tunneling is investigated. Compared with the conventional TFET, the resonant TFET (R-TFET) only exchanges the materials between the source region and channel (drain) region.^[21] Here, the materials used in the source region and channel (drain) region of the R-TFET are In_0.7Ga_0.3As and GaAs_0.35Sb_0.65, respectively. Figure 12 shows the lateral band diagrams of the conventional TFET and the R-TFET. In the R-TFET, there is a narrow triangle quantum well between the source and channel due to the larger electron affinity of In_0.7Ga_0.3As (χ = 4.651 eV) than that of GaAs_0.35Sb_0.65 (χ = 4.07 eV),^[22] which creates a double-barrier band structure^[21] as shown in Fig. 12(b). According to quantum mechanism, there are discrete energy levels in a quantum well. The way of tunneling through the double-barrier via discrete energy levels is resonant tunneling.^[23] The tunneling probability, as a function of tunneling carrier energy, is like Breit–Wigner-type distribution, and can achieve maximum when the energy of tunneling carriers is equal to a quantized energy level. In Fig. 13, the transfer characteristics of the conventional TFET and the R-TFET are plotted. It is obvious that the transfer curve of the R-TFET in the sub-threshold region is much steeper than that of the conventional TFET, which results from the fact that when the energy level of tunneling carriers in the R-TFET aligns with the quantized energy level, the tunneling probability and thus the drain current increases abruptly. The drain current of the R-TFET increases from 10⁻⁸ μA/μm to 10⁻² μA/μm with a gate voltage increase of 110 mV. The minimum SS of the R-TFET is 11 mV/decade and SS is below 20 mV/decade over 2.5 decades of drain current as shown in Fig. 14. The average SS of the R-TFET calculated in a drain current range from 10⁻⁷ μA/μm to 10⁻² μA/μm, is merely 20 mV/decade, 30 mV/decade lower than the conventional TFET. Because of its excellent sub-threshold performance, the R-TFET may have greater potential applications in very low-voltage and low-power though its on-state current is lower than that of the conventional TFET.

Fig. 11.

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	Fig. 11. Curves of SS versus drain current for different material compositions at VDS = 0.5 V, NA = 1020 cm−3, and ND = 1018 cm−3.

Fig. 12.

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	Fig. 12. Energy band diagrams of (a) the conventional TFET and (b) the R-TFET with Lg = 10 nm at VGS = 0 V.

Fig. 13.

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	Fig. 13. Transfer curves of the conventional TFET (C-TFET) and the R-TFET, where VDS = 0.5 V, R = 3 nm, NA = 1020 cm−3, and ND = 5 × 1018 cm−3.

Fig. 14.

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	Fig. 14. Curves of SS versus drain current of the C-TFET and R-TFET, where VDS = 0.5 V, R = 3 nm, NA = 1020 cm−3, and ND = 5 × 1018 cm−3.

The characteristics of cylindrical SG GaAs_x Sb_1−x/In_yGa_1−yAs heterojunction TFET with gate–drain underlap are investigated. The effects of doping concentration, gate–drain underlap, gate length, and the compositions of GaAs_x Sb_1−x and In_yGa_1−yAs on the performance are analyzed. It turns out that better SS can be obtained through lower drain doping concentration and longer gate–drain underlap, and the drain current can be enhanced by modulating the alloy composition or increasing source doping concentration. In addition, a novel TFET called R-TFET is studied based on GaAs_x Sb_1−x/In_yGa_1−yAs staggered-gap heterojunction, and the result shows that the sub-threshold performance is superior to that of the conventional TFET due to its resonant tunneling mechanism. The minimum SS of the R-TEFT is only 11 mV/decade, and its average SS is 20 mV/decade for 5 decades of drain current, 30 mV/decade lower than those of the conventional TFET.